1. Field of the Invention
The present invention relates to a semiconductor storage device and a method for generating a signal for activating an internal circuit thereof.
2. Description of the Prior Art
To generate a sense-amplifier activation signal or a latch capture signal, timing is conventionally generated from a READ command input signal by using only an internal delay circuit. Therefore, it is necessary to optimize the timing by considering the power-supply dependence and temperature dependence of the internal delay circuit and threshold voltage dependence of a transistor and thereby, optimization of the timing has made design difficult.
Moreover, even if timing is set, a temporal position of the timing has been greatly fluctuated when power supply, temperature, or threshold value of a transistor is changed. Therefore, fluctuation from a set value decreases an operation margin.
Particularly, in the case of a synchronous mask ROM, it is necessary to latch the data to be output within a predetermined cycle period and moreover, timing is designed by considering temperature, voltage, and delay of the timing due to a diffusion parameter so that latching of the data is completed in the cycle period. Therefore, design is complex.
FIG. 12 shows a block diagram of a conventional example.
The structure in FIG. 12 comprises a timing generation circuit 22, cells A31 to D34, sense amplifiers A41 to D44, latches A51 to D54, and an output buffer 23. A pulse signal READ generated when inputting a READ command is input to the timing generation circuit 22 and a sense-amplifier activation signal SAEB and a latch capture signal SALT are output.
The sense-amplifier activation signal SAEB is input to the sense amplifiers A41 to D44 and the latch capture signal SALT is input to the latches A51 to D54. Moreover, outputs of the latches A51 to D54 are input to the output buffer 23 so as to be selectively conducted in accordance with select signals BURST0 to BURST3. Data input to the output buffer 23 is output synchronously with an internal clock signal ICLK synchronizing with an external clock.
The timing diagram in FIG. 13 is a timing diagram for explaining a clock of the conventional example in FIG. 12. FIG. 14 shows a timing generation circuit 22 of the conventional example and FIG. 15 shows a timing diagram of the timing generation circuit.
Operations of the conventional example will be described below. FIG.12 is a block diagram of the conventional example and FIG. 13 is a timing diagram of the conventional example. Operations shown in FIG. 12 will be described below.
When inputting a READ command to an external clock CLK, pulse signals RECMDB and READ are generated. These pulse signals do not synchronize with an internal clock ICLK but they generate a sense-amplifier activation signal SAEB and a latch capture signal SALT through the timing generation circuit 22 using delay circuits 24 and 25. That is, timings of the SAEB and SALT do not depend on the timing of the external clock CLK but they determine pulse widths (1 and 2 in FIG. 13). The sense-amplifier activation signal SAEB activates the sense amplifiers A41 to D44 and reads data from the cells A31 to D34 to output the data. The latch capture signal SALT activates the latches A51 to D54 to latch the data output from the sense amplifiers A41 to D44. These operations are performed in a latency (waiting time) period.
Data latched in the latency period is input to the output buffer depending on which one of the signals BURST0 to BURST3 for respectively determining a burst output is selected. FIG. 13 shows a case in which BURST0, BURST1, and BURST2 are selected in order. Therefore, BURST0 is first selected after the latency period and the data in the latch A51 is input to the output buffer. Then, OA0 is output synchronously with an internal clock ICLK. This is a burst period. Because BURST1 is selected next to BURST0, the data in the latch B52 is output at the next cycle and OA1 is output. This is a system of previously completing latching of cell data and outputting the data latched in a burst period every cycle. Therefore, it is necessary to complete latching of the data in the latency period.
Circuit operations of the conventional example for realizing the above mentioned will be described below.
FIG. 14 is a timing generation circuit 22 of the conventional example. Operations of this circuit will be described below by referring to the timing diagram in FIG. 14. When a READ command is input, a pulse is input to a READ terminal in FIG. 14. A sense-amplifier activation signal SAEB is set to `L` level by the pulse signal READ. Then, a pulse shown in FIG. 15 is generated from SAEB and SALT in accordance with delays A24 and B25 (shown by A and B in FIG. 15).
As a result, as shown by the timing diagram in FIG. 15, a sense-amplifier activation signal SAEB and a latch capture signal SALT become pulses not synchronizing with an internal clock ICLK but they are determined by delay A24 and delay B25.
Delays A24 and B25 are generated by using a transistor or a wiring capacitance. However, because the delays A24 and B25 fluctuate due to voltage, temperature, or diffusion parameters, it is difficult to set the delays A24 and B25 when using them as the timings for completing data latching within the latency period.
In case of the above prior art, to generate the timing of a sense-amplifier activation signal or latch capture signal, timing is generated from a READ command input signal by using only an internal delay circuit. Therefore, it is necessary to optimize timing by considering the power supply and temperature dependence of the internal delay circuit and the threshold voltage dependence of a transistor. Therefore, optimization of the timing makes design difficult.
Moreover, even if timing is set, a temporal position of the timing has been greatly fluctuated when power supply, temperature, or threshold value of a transistor is changed. Therefore, fluctuation from a set value decreases an operation margin.
Particularly, in case of a synchronous mask ROM, where it is necessary to latch the data to be output in a predetermined cycle period and to design timing so that latching is completed in the cycle period, it is difficult to design the timing because of a delay due to temperature, voltage, or diffusion parameters.